The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2018
Filed:
May. 31, 2016
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Inventors:
Jia-Rui Hu, Taichung, TW;
Shu-Chuan Chuang, Hsinchu, TW;
Che-Yuan Sun, Hualien County, TW;
Chih-Ming Ke, Hsinchu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); G06F 17/50 (2006.01); H01L 21/768 (2006.01); H01J 37/28 (2006.01); G03F 1/84 (2012.01);
U.S. Cl.
CPC ...
H01L 22/12 (2013.01); G03F 1/84 (2013.01); G06F 17/5068 (2013.01); H01J 37/28 (2013.01); H01L 21/76801 (2013.01);
Abstract
A method provides a design layout having a pattern of features. The design layout is transferred onto a substrate on a semiconductor substrate using a mask. A scanning parameter is determined based on the design layout. An image of the substrate is generated using the determined scanning parameter. A substrate defect is identified by comparing a first number of closed curves in a region of the image and a second number of polygons in a corresponding region of the design layout.