The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Oct. 05, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Jelin Wang, Zhubei, TW;

Ching-Chen Hao, Zhubei, TW;

Yi-Huang Wu, Zhubei, TW;

Meng Yi Sun, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 21/823807 (2013.01); H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 29/165 (2013.01); H01L 29/7834 (2013.01); H01L 29/7848 (2013.01); H01L 29/6656 (2013.01);
Abstract

A device includes a semiconductor substrate, a first Metal-Oxide-Semiconductor (MOS) device, and a second MOS device of a same conductivity as the first MOS device. The first MOS device includes a first gate stack over the semiconductor substrate, and a first stressor adjacent to the first gate stack and extending into the semiconductor substrate. The first stressor and the first gate stack have a first distance. The second MOS device includes a second gate stack over the semiconductor substrate, and a second stressor adjacent to the second gate stack and extending into the semiconductor substrate. The second stressor and the second gate stack have a second distance greater than the first distance.


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