The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Jan. 30, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Sheng-Chau Chen, Tainan, TW;

Cheng-Tai Hsiao, Tainan, TW;

Cheng-Yuan Tsai, Chu-Pei, TW;

Hsun-Chung Kuang, Hsinchu, TW;

Yao-Wen Chang, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 21/311 (2006.01); H01L 21/3105 (2006.01); H01L 43/02 (2006.01); H01L 23/528 (2006.01); H01L 43/08 (2006.01);
U.S. Cl.
CPC ...
H01L 21/31116 (2013.01); H01L 21/31053 (2013.01); H01L 23/528 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 45/1233 (2013.01);
Abstract

A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends upwardly along sidewalls of the bottom electrode, the switching dielectric, and the top electrode. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The lower etch stop layer is made of a material different from the sidewall spacer layer and protects the top electrode from damaging during manufacturing processes. A method for manufacturing the memory cell is also provided.


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