logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10163522 B1

PDFFull Text
Date of Patent:
Dec. 25, 2018

Filed:

Oct. 15, 2015

Test line letter for embedded non-volatile memory technology

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsun-Chu, TW;

Inventors:

Jui-Tsung Lien, Hsinchu, TW;

Fang-Lan Chu, Taichung, TW;

Hong-Da Lin, Taipei, TW;

Wei Cheng Wu, Zhubei, TW;

Ku-Ning Chang, Taichung, TW;

Yu-Chen Wang, Huwei Township, TW;

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Attorney:

Eschweiler & Potashnik, LLC

Primary Examiner:

Bradley Smith

Assistant Examiner:

David J Goodwin

Int. Cl.
CPC ...
G02F 1/1333 (2006.01); H01L 23/544 (2006.01); G11C 29/02 (2006.01); G01R 31/28 (2006.01); H01L 21/28 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 27/11568 (2017.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 27/11526 (2017.01); H01L 27/11573 (2017.01); G11C 29/56 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G11C 29/025 (2013.01); G01R 31/2884 (2013.01); H01L 21/28282 (2013.01); H01L 21/32133 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/544 (2013.01); H01L 27/11568 (2013.01); H01L 29/42344 (2013.01); H01L 29/4916 (2013.01); H01L 29/513 (2013.01); G11C 2029/5602 (2013.01); H01L 22/34 (2013.01); H01L 27/11526 (2013.01); H01L 27/11573 (2013.01); H01L 2223/5446 (2013.01); H01L 2223/54406 (2013.01); H01L 2223/54453 (2013.01);
Abstract

The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, the substrate has a semiconductor substrate. A test line letter structure is arranged over the semiconductor substrate and has one or more trenches vertically extending between an upper surface of the test letter structure and a lower surface of the test line letter structure. The one or more trenches are arranged within the test line letter structure to form an opening in the upper surface of the test line structure that has a shape of an alpha-numeric character.

Find Patent Forward Citations

Loading…