The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Oct. 10, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Mark A. Burns, Essex Junction, VT (US);

Douglas S. Dewey, Highgate, VT (US);

Nazmul Habib, South Burlington, VT (US);

Daniel D. Reinhardt, Milton, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05B 19/042 (2006.01); G01R 31/28 (2006.01); G05B 17/02 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G05B 19/0428 (2013.01); G01R 31/2856 (2013.01); G01R 31/2875 (2013.01); G05B 17/02 (2013.01); G05B 2219/45031 (2013.01); H01L 22/30 (2013.01);
Abstract

A method for applying stress conditions to integrated circuit device samples during accelerated stress testing may include partitioning each of the integrated circuit device samples into a first region having a first functional element, partitioning each of the integrated circuit device samples into at least one second region having at least one second functional element, applying a first stress condition to the first region having the first element, applying a second stress condition to the at least one second region having the at least one second element, determining a first portion of the integrated circuit device samples that functionally failed based on the first stress condition, and determining a second portion of the integrated circuit device samples that functionally failed based on the second stress condition. An acceleration model parameter is derived based on the determining of the first and second portion of the integrated circuit samples that functionally failed.


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