The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

Jul. 31, 2017
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Gloria Yang, Higashihiroshima, JP;

Suraj J. Mathew, Boise, ID (US);

Raghunath Singanamalla, Boise, ID (US);

Vinay Nair, Boise, ID (US);

Scott J. Derner, Boise, ID (US);

Michael Amiel Shore, Boise, ID (US);

Brent Keeth, Boise, ID (US);

Fatma Arzum Simsek-Ege, Boise, ID (US);

Diem Thy N. Tran, Garden City, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 49/02 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); G11C 11/403 (2006.01); H01L 23/528 (2006.01); H01L 27/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/108 (2013.01); G11C 11/403 (2013.01); H01L 28/90 (2013.01); H01L 29/42376 (2013.01); H01L 29/7827 (2013.01); H01L 23/528 (2013.01); H01L 27/0688 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01);
Abstract

Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.


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