The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 18, 2018
Filed:
Aug. 07, 2017
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/02 (2006.01); H01L 21/28 (2006.01); H02H 9/04 (2006.01); H01L 27/088 (2006.01); H01L 29/10 (2006.01); H01L 21/8234 (2006.01); H01L 23/60 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0266 (2013.01); H01L 21/28123 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 23/60 (2013.01); H01L 27/0207 (2013.01); H01L 27/0292 (2013.01); H01L 27/0886 (2013.01); H01L 29/1095 (2013.01); H01L 29/66545 (2013.01); H02H 9/046 (2013.01);
Abstract
An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, wherein each active region is substantially uniform in length. The first gate device and the second device are formed over a first well having a first conductivity type and the dummy gate is formed over a second well having a second conductivity type.