The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

Dec. 07, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Pu-Fang Chen, Hsinchu, TW;

Victor Y. Lu, Foster City, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 21/324 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 25/065 (2006.01); H01L 29/32 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/324 (2013.01); H01L 21/76852 (2013.01); H01L 21/76898 (2013.01); H01L 23/53238 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 29/32 (2013.01); H01L 2225/06541 (2013.01);
Abstract

In a method of manufacturing a semiconductor device, a thermal treatment is performed on a substrate, thereby forming a defect free layer in an upper layer of the substrate, where a remaining layer of the substrate is a bulk layer. A density of defects in the bulk layer is equal to or more than 1×10cm, where the defects are bulk micro defects. An electronic device is formed over the defect free layer. An opening is formed in the defect free layer such that the opening does not reach the bulk layer. The opening is filled with a conductive material, thereby forming a via. The bulk layer is removed so that a bottom part of the via is exposed. A density of defects in the defect free layer is less than 100 cm.


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