The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

Jun. 19, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Puneet H. Suvarna, Menands, NY (US);

Steven Bentley, Menands, NY (US);

Mark V. Raymond, Latham, NY (US);

Peter M. Zeitzoff, Clifton Park, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/285 (2006.01); H01L 27/088 (2006.01); H01L 29/45 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823418 (2013.01); H01L 21/28518 (2013.01); H01L 21/823437 (2013.01); H01L 21/823487 (2013.01); H01L 27/088 (2013.01); H01L 29/0847 (2013.01); H01L 29/42392 (2013.01); H01L 29/45 (2013.01); H01L 29/7827 (2013.01); H01L 29/7853 (2013.01); H01L 2029/7858 (2013.01);
Abstract

Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.


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