The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

Nov. 28, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yi-Shan Chen, Tainan, TW;

Chan-Syun David Yang, Taipei, TW;

Li-Te Lin, Hsinchu, TW;

Pinyen Lin, Rochester, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/033 (2006.01); H01L 23/528 (2006.01); H01L 21/32 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76804 (2013.01); H01L 21/0331 (2013.01); H01L 21/0337 (2013.01); H01L 21/31122 (2013.01); H01L 21/31144 (2013.01); H01L 21/32 (2013.01); H01L 23/5283 (2013.01); H01L 21/02115 (2013.01); H01L 21/02282 (2013.01); H01L 21/0332 (2013.01);
Abstract

A method of forming a semiconductor structure is provided. In this method, a semiconductor substrate is provided. A SoC layer is formed on the semiconductor substrate. A hard mask layer is formed over the SoC layer. The hard mask layer is patterned to expose a portion of the SoC layer. At least one opening is formed on the portion of the SoC layer using an ALE operation, thereby enabling the remaining portion of the SoC layer adjacent to the at least one opening to have a re-entrant angle included between a sidewall of the SoC layer and a bottom of the SoC layer.


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