The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2018

Filed:

Mar. 16, 2017
Applicants:

Stmicroelectronics International N.v., Schiphol, NL;

Stmicroelectronics SA, Montrouge, FR;

Inventors:

Alok Kumar Tripathi, Ghaziabad, IN;

Amit Verma, Sadhaura, IN;

Pascal Urard, Theys, FR;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/012 (2006.01); H03K 3/356 (2006.01); H03K 19/00 (2006.01); H03K 3/3562 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356104 (2013.01); H03K 3/012 (2013.01); H03K 3/35625 (2013.01); H03K 19/0002 (2013.01);
Abstract

A synchronous retention flip-flop circuit includes a first circuit module powered by an interruptible power source and a second circuit module powered by a permanent power source. The first circuit module includes a first latch circuit and a second latch circuit which are configured to store at least one datum while the interruptible power source is supplying power. A transmission circuit operates to deliver the at least one datum to the second circuit module before an interruption of the interruptible power source. The second circuit module preserves the at least one datum during the interruption. Following an end of the interruption, a restoring circuit transfers the at least one datum from the second circuit module to the first circuit module via a single one of the first and second latch circuits.


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