The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2018
Filed:
Jul. 29, 2016
Stmicroelectronics International N.v., Amsterdam, NL;
Venkata Narayanan Srinivasan, Gautam Budh Nagar District, IN;
Tripti Gupta, Noida, IN;
STMicroelectronics International N.V., Schiphol, NL;
Abstract
A logic built-in self-test (LBIST) circuit implements a pipeline scan enable launch on shift (LOS) feature. A first scan chain flip-flop has a scan enable input configured to receive a first scan enable signal. A logic circuit has a first input coupled to a data output of the first scan chain flip-flop and a second input coupled to receive the first scan enable signal. A second scan chain flip-flop has a scan input coupled to a scan output of the first scan chain flip-flop. A scan enable input of the second scan chain flip-flop is coupled to receive a second scan enable signal generated at an output of the logic circuit. The first and second scan chain flip-flops are clocked by a same clock signal.