The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

Sep. 02, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Tonia G Morris, Irmo, SC (US);

Ying Zhou, Portland, OR (US);

John V. Lovelace, Irmo, SC (US);

Alberto David Perez Guevara, Zapopan, MX;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); G11C 7/00 (2006.01); G11C 29/02 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0041 (2013.01); G11C 7/00 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); H04L 7/0004 (2013.01); H04L 7/0008 (2013.01); H04L 7/0037 (2013.01); H04L 7/0331 (2013.01);
Abstract

Embodiments are generally directed to signal phase optimization in memory interface training. An embodiment of an apparatus includes an interface for at least one signal; and interface training logic capable of automatically adjusting a phase relationship between the signal and a strobe or clock, including establishing a phase delay of the signal and a phase delay of the strobe or clock for training of the interface, wherein the interface training logic is capable of determining a phase delay reduction for the signal subsequent to measurement of an eye margin for the signal, the phase delay reduction to retain a sufficient delay to maintain the eye margin for sampling of the signal.


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