The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

May. 23, 2017
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Bin Tang, Singapore, SG;

Jubao Zhang, Singapore, SG;

Xiaofei Han, Singapore, SG;

Chao Jiang, Singapore, SG;

Hong Liao, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/283 (2006.01); H01L 21/762 (2006.01); H01L 27/11531 (2017.01); H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 27/11521 (2017.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66825 (2013.01); H01L 21/76229 (2013.01); H01L 21/823437 (2013.01); H01L 27/11521 (2013.01); H01L 27/11531 (2013.01); H01L 29/7881 (2013.01); H01L 21/823431 (2013.01);
Abstract

A method of fabricating a floating gate includes providing a substrate divided into a cell region and a logic region. A silicon oxide layer and a silicon nitride layer cover the cell region and the logic region. Numerous STIs are formed in the silicon nitride layer, the silicon oxide layer, and the substrate. Later, the silicon nitride layer within the cell region is removed to form one recess between the adjacent STIs within the cell region while the silicon nitride layer within the logic region remains. Subsequently, a conductive layer is formed to fill the recess. The conductive layer is thinned to form a floating gate.


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