The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 2018
Filed:
Jan. 10, 2017
Apple Inc., Cupertino, CA (US);
Phillip R. Sommer, Newark, CA (US);
Shankar Pennathur, San Jose, CA (US);
Meng Chi Lee, Los Altos, CA (US);
Shakti S. Chauhan, Cupertino, CA (US);
Yanfeng Chen, San Ramon, CA (US);
Apple Inc., Cupertino, CA (US);
Abstract
Electrical components may be packaged using system-in-package configurations or other component packages. Integrated circuit dies and other electrical components may be soldered or otherwise mounted on printed circuits. A layer of encapsulant may be used to encapsulate the integrated circuits. A shielding layer may be formed on the encapsulant layer to shield the integrate circuits. The shielding layer may include a sputtered metal seed layer and an electroplated layer of magnetic material. The electroplated layer may be a magnetic material that has a high permeability such as permalloy or mu metal to provide magnetic shielding for the integrated circuits. Integrated circuits may be mounted on one or both sides of the printed circuit. A temporary carrier and sealant may be used to hold the encapsulated integrated circuits during electroplating.