The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2018

Filed:

Oct. 11, 2016
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Chun-Ming Chen, New Taipei, TW;

Man-Tang Wu, Hsinchu County, TW;

Jeng-Wei Yang, Hsinchu County, TW;

Chien-Sheng Su, Saratoga, CA (US);

Nhan Do, Saratoga, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 27/11521 (2017.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/28273 (2013.01); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01); G11C 16/0408 (2013.01);
Abstract

A method of forming a non-volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region. A tunnel oxide layer is formed around the sharp edge. An erase gate is formed over the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer. A word line gate is formed over a second portion of the channel region which is adjacent to the second region. The forming of the word line gate is performed after the forming of the tunnel oxide layer and the erase gate.


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