The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2018

Filed:

Dec. 29, 2016
Applicant:

Asm Ip Holding B.v., Almere, NL;

Inventors:

Harald Profijt, Leuven, BE;

Qi Xie, Leuven, BE;

Jan Willem Maes, Wilrijk, BE;

David Kohen, Leuven, BE;

Assignee:

ASM IP HOLDING B.V., Almere, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/225 (2006.01); H01L 29/66 (2006.01); H01L 29/161 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 21/223 (2006.01); H01L 21/768 (2006.01); H01L 21/385 (2006.01);
U.S. Cl.
CPC ...
H01L 21/225 (2013.01); H01L 21/223 (2013.01); H01L 21/2251 (2013.01); H01L 21/2256 (2013.01); H01L 21/385 (2013.01); H01L 21/76858 (2013.01); H01L 29/0676 (2013.01); H01L 29/1033 (2013.01); H01L 29/161 (2013.01); H01L 29/66666 (2013.01);
Abstract

In some embodiments, a compound semiconductor is formed by diffusion of semiconductor species from a source semiconductor layer into semiconductor material in a substrate. The source semiconductor layer may be an amorphous or polycrystalline structure, and provides a source of semiconductor species for later diffusion into the other semiconductor material. Advantageously, such a semiconductor layer may be more conformal than an epitaxially grown, crystalline semiconductor layer. As a result, this more conformal semiconductor layer acts as a uniform source of the semiconductor species for diffusion into the semiconductor material in the substrate. In some embodiments, an interlayer is formed between the source semiconductor layer and the substrate, and then the interlayer is trimmed before depositing the source semiconductor layer. In some other embodiments, the source semiconductor layer is deposited directly on the substrate, and has an amorphous or polycrystalline structure.


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