The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 2018
Filed:
Dec. 26, 2015
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Randy J. Koval, Boise, ID (US);
Hiroyuki Sanda, Palo Alto, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); G11C 16/26 (2006.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 27/11524 (2017.01); H01L 27/1157 (2017.01); G11C 16/08 (2006.01); H01L 27/11526 (2017.01); H01L 27/11573 (2017.01); H01L 21/3213 (2006.01); H01L 27/11519 (2017.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); H01L 21/32133 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01);
Abstract
An apparatus is described having a memory. The memory includes a vertical stack of storage cells, where, a first storage node at a lower layer of the vertical stack has a different structural design than a second storage node at a higher layer of the vertical stack.