The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2018

Filed:

Oct. 17, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Hsun-Peng Lin, Nanzhuang Township, Miaoli County, TW;

Hsin-Kuo Chang, Hsinchu, TW;

Han-Chih Chung, Pingzhen, TW;

Yueh-Chih Wang, Zhudong Township, Hsinchu County, TW;

Chi-Jen Hsieh, Toufen Township, Miaoli County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B08B 7/00 (2006.01); B08B 7/04 (2006.01); H01L 21/02 (2006.01); H01L 21/67 (2006.01); H01L 21/68 (2006.01); H01L 23/544 (2006.01); B08B 1/00 (2006.01); B08B 15/04 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0209 (2013.01); B08B 1/002 (2013.01); B08B 15/04 (2013.01); H01L 21/02057 (2013.01); H01L 21/02087 (2013.01); H01L 21/67046 (2013.01); H01L 21/68 (2013.01); H01L 23/544 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54453 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The present disclosure provides a method of cleaning a semiconductor wafer during a process of fabricating a semiconductor device. The method includes loading a semiconductor wafer into a wafer handling system. The method includes removing contaminant particles from an edge region of the wafer from the back side, wherein alignment marks are located in the edge region. The method includes collecting the removed contaminant particles and discarding the collected contaminant particles out of the wafer handling system. The disclosure also provides an apparatus for fabricating a semiconductor device. The apparatus includes a wafer cleaning device that is operable to clean a predetermined region of the wafer on the back surface thereof. The predetermined region of the wafer at least partially overlaps with one or more alignment marks.


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