The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2018

Filed:

May. 31, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Li-Jung Liu, Hsinchu, TW;

Chih-Pin Tsao, Hsinchu County, TW;

Chia-Wei Soong, Taoyuan, TW;

Jyh-Huei Chen, Hsinchu, TW;

Shu-Hui Wang, Hsinchu, TW;

Shih-Hsun Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 21/67 (2006.01); H01L 21/311 (2006.01); H01L 21/027 (2006.01); H01J 37/32 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67069 (2013.01); H01J 37/32 (2013.01); H01L 21/0274 (2013.01); H01L 21/3065 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/67063 (2013.01); H01L 2924/12042 (2013.01);
Abstract

A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent. An example benefit includes reduction or elimination of diffusion of fluorine contaminants from a gate metal fill layer into its underlying layers and from conductive layers into diffusion barrier layers and silicide layers of source/drain contact structures and consequently, the reduction of the negative impact of these fluorine contaminants on device performance.


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