The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Mar. 22, 2016
Applicants:

Sug-hyun Sung, Yongin-si, KR;

Jung-gun You, Ansan-si, KR;

Gi-gwan Park, Suwon-si, KR;

Inventors:

Sug-hyun Sung, Yongin-si, KR;

Jung-gun You, Ansan-si, KR;

Gi-gwan Park, Suwon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/76229 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 29/0649 (2013.01); H01L 29/66818 (2013.01); H01L 29/7843 (2013.01); H01L 29/7854 (2013.01);
Abstract

Integrated circuit devices are provided. The devices may include first and second fin-shaped channel regions protruding from a substrate, and the first and second fin-shaped channel regions may define a recess therebetween. The devices may also include an isolation layer in a lower portion of the recess. The isolation layer may include a first stress liner extending along a side of the first fin-shaped channel region, a second stress liner extending along a side of the second fin-shaped channel region and an insulation liner between the first stress liner and the side of the first fin-shaped channel region and between the second stress liner and the side of the second fin-shaped channel region. The devices may further include a gate insulation layer on surfaces of upper portions of the first and second fin-shaped channel regions and a gate electrode layer on the gate insulation layer.


Find Patent Forward Citations

Sung, Sug-hyun. (2018). Integrated circuit (ic) devices including stress inducing layers (U.S. Patent No. 10103142). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10103142

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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