The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Mar. 21, 2017
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chung-Yu Huang, Tainan, TW;

Kuan-Cheng Su, Taipei, TW;

Tien-Hao Tang, Hsinchu, TW;

Ping-Jui Chen, Pingtung County, TW;

Po-Ya Lai, Changhua County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01); H01L 27/02 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0277 (2013.01); H01L 29/0619 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/42372 (2013.01); H01L 29/7816 (2013.01); H01L 29/7851 (2013.01);
Abstract

An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the source region, and at least a second doped region formed in the drain region. The source region, the drain region and the second doped region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The second doped region is electrically connected to the first doped region. The gate set includes at least a first gate structure, a second gate structure, and a third gate structure.


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