The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Mar. 29, 2017
Applicant:

Intel Ip Corporation, Santa Clara, CA (US);

Inventors:

Quan Qi, Beaverton, OR (US);

Brian R. Butcher, Queen Creek, AZ (US);

Carlton E. Hanna, Santa Clara, CA (US);

Hong Wei Hu, Gilbert, AZ (US);

Assignee:

Intel IP Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/433 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4334 (2013.01); H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/0652 (2013.01); H01L 2924/18165 (2013.01);
Abstract

Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include a die disposed on a first substrate, at least one component adjacent the die on the first substrate, a molding material on the die and the at least one component, wherein the die and the at least one component are completely embedded in the molding material, a second substrate, wherein the first substrate is disposed on a top surface of the second substrate, and at least one communication structure disposed on a surface of the second substrate.


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