The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Jan. 29, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chia-Wei Lu, Hsinchu, TW;

Hon-Lin Huang, Hsinchu, TW;

Hung-Chih Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B05C 13/00 (2006.01); H01L 21/67 (2006.01); C23C 18/16 (2006.01); B05C 11/06 (2006.01); H01L 21/673 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67196 (2013.01); B05C 11/06 (2013.01); C23C 18/1691 (2013.01); H01L 21/67109 (2013.01); H01L 21/67201 (2013.01); H01L 21/67303 (2013.01);
Abstract

A chamber includes a sidewall, a cooling pipe, and an external pipe. The cooling pipe includes a first segment extending along the sidewall of the chamber, and includes multiple purge nozzles. The external pipe extends to inside the chamber and is connected to the first segment of the cooling pipe. A semiconductor processing station includes a central transfer chamber, a load lock chamber, and a cooling stage. The load lock chamber and the cooling stage are disposed adjacent to the central transfer chamber. The load lock chamber is adapted to contain a wafer carrier having multiple wafers. The central transfer chamber communicates between the cooling stage and the load lock chamber to transfer a wafer between the cooling stage and the load lock chamber. A semiconductor process using the semiconductor processing station is also provided.


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