The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2018

Filed:

Sep. 11, 2015
Applicant:

Sandisk 3d Llc, Milpitas, CA (US);

Inventors:

Shin Kikuchi, Yokkaichi, JP;

Kazushi Komeda, Yokkaichi, JP;

Takuya Futase, Yokkaichi, JP;

Teruyuki Mine, Yokkaichi, JP;

Seje Takaki, Yokkaichi, JP;

Eiji Hayashi, Yokkaichi, JP;

Toshihide Tobitsuka, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2481 (2013.01); H01L 27/249 (2013.01); H01L 27/2436 (2013.01); H01L 27/2454 (2013.01); H01L 45/08 (2013.01); H01L 45/1226 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01); H01L 45/16 (2013.01); H01L 45/1616 (2013.01); H01L 45/1633 (2013.01);
Abstract

An alternating material stack of insulator lines and first electrically conductive material layers is formed over a substrate, and is patterned to provide alternating stacks of insulating layers and first electrically conductive lines. A metal can be selectively deposited on the physically exposed sidewalls of the first electrically conductive material layers to form metal lines, while not growing from the surfaces of the insulator lines. The metal lines are oxidized to form metal oxide lines that are self-aligned to the sidewalls of the first electrically conductive lines. Vertically extending second electrically conductive lines can be formed as a two-dimensional array of generally pillar-shaped structures between the alternating stacks of the insulator lines and the first electrically conductive lines. Each portion of the metal oxide lines at junctions of first and second electrically conductive lines constitute a resistive memory element for a resistive random access memory (ReRAM) device.


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