The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2018

Filed:

Aug. 28, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

David R. Tipple, Leander, TX (US);

Alistair J. Gorman, Broughty Ferry, GB;

Anis M. Jarrar, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); G01R 31/28 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2896 (2013.01); G01R 31/2884 (2013.01); G01R 31/2886 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01);
Abstract

A wafer structure has a plurality of semiconductor die. Each semiconductor die includes circuitry, a test pad for use in testing the circuitry, and a plurality of external pins. The test pad includes first, second, third, and fourth metal lines, a via, and a metal cover that receives a probe. The first and second metal lines are in a first metal layer and run in parallel, are insulated from each other, and are adjacent. The third and fourth metal lines are in a second metal layer run in parallel, are insulated from each other, and run orthogonal to the first and second metal lines. The first via is coupled to the first metal line and the third metal line. One or more external pins are connected to the metal cover.


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