The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2018
Filed:
Aug. 20, 2015
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Po-Chi Wu, Zhubei, TW;
Chai-Wei Chang, New Taipei, TW;
Jung-Jui Li, Hsinchu, TW;
Ya-Lan Chang, Toufen Township, TW;
Yi-Cheng Chao, Lukang Township, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 21/321 (2006.01); H01L 21/3213 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4958 (2013.01); H01L 21/02074 (2013.01); H01L 21/28079 (2013.01); H01L 21/28088 (2013.01); H01L 21/3212 (2013.01); H01L 21/32133 (2013.01); H01L 21/32135 (2013.01); H01L 21/32136 (2013.01); H01L 29/4966 (2013.01); H01L 29/7851 (2013.01);
Abstract
A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.