The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2018

Filed:

Dec. 29, 2017
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Wei-Yu Chen, New Taipei, TW;

Tien-Chung Yang, Hsinchu, TW;

An-Jhih Su, Taoyuan, TW;

Hsien-Wei Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 25/07 (2006.01); H01L 49/02 (2006.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 21/56 (2006.01); H01L 25/00 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 25/071 (2013.01); H01L 21/565 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/3128 (2013.01); H01L 23/5226 (2013.01); H01L 24/06 (2013.01); H01L 24/49 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 28/40 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/48091 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06586 (2013.01);
Abstract

A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device.


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