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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10083982 B1

PDFFull Text
Date of Patent:
Sep. 25, 2018

Filed:

Apr. 25, 2017

Three-dimensional memory device having select gate electrode that is thicker than word lines and method of making thereof

Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Keisuke Shigemura, Yokkaichi, JP;

Junichi Ariyoshi, Yokkaichi, JP;

Masanori Tsutsumi, Yokkaichi, JP;

Michiaki Sano, Yokkaichi, JP;

Yanli Zhang, San Jose, CA (US);

Raghuveer S. Makala, Campbell, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:

The Marbury Law Group PLLC

Primary Examiner:

Maliheh Malek

Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 29/423 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 27/11524 (2017.01); H01L 21/311 (2006.01); H01L 27/1157 (2017.01); H01L 27/11526 (2017.01); H01L 27/11573 (2017.01); H01L 27/11519 (2017.01); H01L 27/11565 (2017.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/28008 (2013.01); H01L 21/31111 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/53266 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 29/4234 (2013.01); H01L 29/42324 (2013.01);
Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.

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