The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2018

Filed:

Nov. 27, 2017
Applicant:

Unimicron Technology Corp., Taoyuan, TW;

Inventors:

Ming-Hao Wu, Taoyuan, TW;

Shu-Sheng Chiang, Taipei, TW;

Wei-Ming Cheng, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H05K 3/00 (2006.01); H05K 1/11 (2006.01); H05K 3/46 (2006.01); H05K 1/02 (2006.01); H05K 1/09 (2006.01); H05K 3/40 (2006.01);
U.S. Cl.
CPC ...
H05K 1/111 (2013.01); H05K 1/0296 (2013.01); H05K 1/0298 (2013.01); H05K 1/09 (2013.01); H05K 1/115 (2013.01); H05K 3/0047 (2013.01); H05K 3/0073 (2013.01); H05K 3/4038 (2013.01); H05K 3/4092 (2013.01); H05K 3/4644 (2013.01); H05K 3/4697 (2013.01); H05K 1/0266 (2013.01); H05K 2201/094 (2013.01); H05K 2201/09036 (2013.01); H05K 2201/09563 (2013.01); H05K 2201/09781 (2013.01); H05K 2203/0376 (2013.01); H05K 2203/163 (2013.01);
Abstract

A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening communicating the cavity and a pad of the first patterned circuit layer is located in the opening. A hole diameter of the opening is smaller than a hole diameter of cavity. An inner surface of the inner dielectric layer exposed by the cavity and a top surface of the pad are coplanar or have a height difference.


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