The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2018

Filed:

Feb. 03, 2016
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Danny Shum, Poughkeepsie, NY (US);

Fook Hong Lee, Singapore, SG;

Yung Fu Alfred Chong, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/792 (2006.01); H01L 29/78 (2006.01); G11C 16/00 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 27/11568 (2017.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); G11C 16/00 (2013.01); G11C 16/0425 (2013.01); H01L 27/11568 (2013.01); H01L 29/42344 (2013.01); H01L 29/66833 (2013.01); H01L 29/7816 (2013.01); H01L 29/7831 (2013.01); H01L 29/7835 (2013.01);
Abstract

Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes providing a substrate prepared with a memory cell region. A first gate structure is formed on the memory cell region. An isolation layer is formed on the substrate and over the first gate structure. A second gate structure is formed adjacent to and separated from the first gate structure by the isolation layer. The first and second gate structures are processed to form at least one split gate structure with first and second adjacent gates. Asymmetrical source and drain regions are provided adjacent to first and second sides of the split gate structure.


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