The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2018

Filed:

Jun. 05, 2017
Applicant:

Novatek Microelectronics Corp., Hsinchu, TW;

Inventors:

Wen-Ching Huang, Hsinchu, TW;

Chien-Chen Ko, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/373 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 21/48 (2006.01); B32B 9/00 (2006.01); B32B 7/12 (2006.01); B32B 37/14 (2006.01); B32B 37/12 (2006.01);
U.S. Cl.
CPC ...
H01L 23/373 (2013.01); B32B 7/12 (2013.01); B32B 9/007 (2013.01); B32B 37/12 (2013.01); B32B 37/14 (2013.01); H01L 21/481 (2013.01); H01L 23/315 (2013.01); H01L 23/3142 (2013.01); H01L 23/367 (2013.01); H01L 23/49838 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); B32B 2457/00 (2013.01); H01L 2224/32225 (2013.01);
Abstract

A chip on film package includes a base film, a patterned circuit layer, a solder resist layer, a chip and a graphite sheet. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The solder resist layer partially covers the patterned circuit layer. The chip is disposed on the mounting region and electrically connected to the patterned circuit layer. The graphite sheet covers at least a part of the solder resist layer, wherein an outer edge of the graphite sheet is substantially aligned with an outer edge of the solder resist layer.


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