The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2018

Filed:

Jul. 26, 2016
Applicants:

International Business Machines Corporation, Armonk, NY (US);

Stmicroelectronics, Inc., Coppell, TX (US);

Inventors:

Hong He, Schenectady, NY (US);

James Kuss, Guilderland, NY (US);

Nicolas Loubet, Hudson, NY (US);

Junli Wang, Singerlands, NY (US);

Assignees:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/324 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 29/161 (2006.01);
U.S. Cl.
CPC ...
H01L 21/845 (2013.01); H01L 21/0217 (2013.01); H01L 21/02532 (2013.01); H01L 21/30604 (2013.01); H01L 21/324 (2013.01); H01L 21/823821 (2013.01); H01L 21/823857 (2013.01); H01L 21/823864 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01); H01L 27/1211 (2013.01); H01L 29/161 (2013.01);
Abstract

A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon layer and the SiGe layer and filling between the fin structures with a dielectric fill. Trenches are formed to expose end portions of the fin structures. A first region of the fin structures is blocked off. The SiGe layer of the fin structures of a second region is removed by selectively etching the fin structures from the end portions to form voids, which are filled with dielectric material. The silicon layer of the fin structures is exposed. The SiGe layer in the first region is thermally oxidized to drive Ge into the silicon layer to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region.


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