The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2018
Filed:
Oct. 27, 2017
United Microelectronics Corp., Hsin-Chu, TW;
Chun-Yen Tseng, Tainan, TW;
Ching-Cheng Lung, Tainan, TW;
Yu-Tse Kuo, Tainan, TW;
Chun-Hsien Huang, Tainan, TW;
Chien-Hung Chen, Taipei, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Abstract
The present invention provides a layout pattern of a memory device composed of static random access memory (SRAM), comprising four memory units located on a substrate, each memory unit being located in a non-rectangular region, the four non-rectangular regions combine a rectangular region, wherein each memory unit comprises a first inverter comprising a first pull-up transistor (PL) and a first pull-down transistor (PD), a second inverter comprises a second pull-up transistor (PL) and a second pull-down transistor (PD), an access transistor (PG) and a switching transistor (SW), wherein the source of the PG is coupled to an input terminal of the first inverter and a drain of the SW, a source of the SW is coupled to an output of the second inverter, wherein the PD, the PD, the SW, and the PG comprise a first diffusion region, the PLand the PLcomprise a second diffusion region.