The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2018

Filed:

Mar. 28, 2016
Applicant:

Stats Chippac, Ltd., Singapore, SG;

Inventors:

Byung Tai Do, Singapore, SG;

Arnel Senosa Trasporto, Singapore, SG;

Assignee:

STATS ChipPAC Pte. Ltd., Singapore, SG;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/60 (2006.01); H01L 23/538 (2006.01); H01L 21/56 (2006.01); H01L 21/50 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/03 (2006.01); H01L 25/10 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/11 (2013.01); H01L 21/561 (2013.01); H01L 23/49811 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/03 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/5389 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 24/97 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16113 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/94 (2013.01); H01L 2224/97 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19105 (2013.01); H01L 2924/19106 (2013.01);
Abstract

A semiconductor device comprises a first semiconductor package including a first interconnect structure extending over a surface of the first semiconductor package. The first semiconductor package includes an interposer and a second semiconductor die disposed over the interposer. A second encapsulant is deposited over the interposer and second semiconductor die. A first semiconductor die is disposed over the surface of the first semiconductor package. A second interconnect structure extends from the first semiconductor die opposite the first semiconductor package. A first encapsulant is deposited over the first semiconductor package and first semiconductor die. A portion of the first encapsulant over the first interconnect structure and second interconnect structure is removed. A discrete component is disposed on the surface of the first semiconductor package. A build-up interconnect structure is formed over the first semiconductor package and first semiconductor die. The first semiconductor package includes a molded laser package.


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