The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2018

Filed:

Jan. 09, 2018
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Malcolm J. Bevan, Dallas, TX (US);

Haowen Bu, Plano, TX (US);

Hiroaki Niimi, Tokyo, JP;

Husam N. Alshareef, Murphy, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01J 37/00 (2006.01); H01L 21/28 (2006.01); C23C 16/455 (2006.01); C23C 16/458 (2006.01); H01J 37/32 (2006.01); H01L 21/02 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28158 (2013.01); C23C 16/4582 (2013.01); C23C 16/45557 (2013.01); H01J 37/32752 (2013.01); H01J 37/32825 (2013.01); H01J 37/32899 (2013.01); H01L 21/0234 (2013.01); H01L 21/02181 (2013.01); H01L 21/02326 (2013.01); H01L 21/02332 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01J 2237/3321 (2013.01);
Abstract

Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.


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