The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2018
Filed:
Apr. 28, 2009
Applicants:
Amit Paul, Sunnyvale, CA (US);
Mohamed N. Darwish, Campbell, CA (US);
Inventors:
Amit Paul, Sunnyvale, CA (US);
Mohamed N. Darwish, Campbell, CA (US);
Assignee:
MAXPOWER SEMICONDUCTOR INC., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78624 (2013.01); H01L 29/0634 (2013.01); H01L 29/408 (2013.01); H01L 29/7824 (2013.01); H01L 29/7825 (2013.01); H01L 29/0653 (2013.01); H01L 29/0696 (2013.01); H01L 29/0873 (2013.01); H01L 29/0878 (2013.01); H01L 29/0886 (2013.01); H01L 29/42368 (2013.01);
Abstract
A lateral SOI device may include a semiconductor channel region connected to a drain region by a drift region. An insulation region on the drift layer is positioned between the channel region and the drain region. Permanent charges may be embedded in the insulation region sufficient to cause inversion in the insulation region. The semiconductor layer also overlies a global insulation layer, and permanent charges are preferably embedded in at least selected areas of this insulation layer too.