The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2018

Filed:

Aug. 04, 2017
Applicants:

Fuji Electric Co., Ltd., Kawasaki-shi, Kanagawa, JP;

Sumitomo Electric Industries, Ltd., Osaka-shi, Osaka, JP;

Inventors:

Yusuke Kobayashi, Tsukuba, JP;

Hiromu Shiomi, Tsukuba, JP;

Shinya Kyogoku, Tsukuba, JP;

Shinsuke Harada, Tsukuba, JP;

Akimasa Kinoshita, Matsumoto, JP;

Assignees:

FUJI ELECTRIC CO., LTD., Kawasaki-Shi, Kanagawa, JP;

SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka-Shi, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 21/04 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0634 (2013.01); H01L 21/0455 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/7811 (2013.01); H01L 29/7813 (2013.01); H01L 21/823487 (2013.01); H01L 29/66287 (2013.01); H01L 29/66734 (2013.01);
Abstract

An active region through which current flows in a semiconductor device includes an n-type silicon carbide epitaxial layer formed on a front surface of an n-type silicon carbide semiconductor substrate; a p-type layer becoming a channel region; a trench formed so as to be in contact with a p-type layer and having an oxide film and a gate electrode embedded therein; a p-type layer arranged beneath the trench and between trenches; an n-type layer in contact with the p-type layer, a p-type layer, and the trench, and arranged in contact with a p-type layer or on a surface side of the semiconductor substrate; an n-type layer in contact with the n-type silicon carbide epitaxial layer and the p-type layer, and having an impurity concentration higher than that of the n-type layer and that of the n-type silicon carbide epitaxial layer.


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