The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2018

Filed:

Jun. 12, 2014
Applicant:

Monolith Semiconductor, Inc., Ithaca, NY (US);

Inventors:

Kiran Chatty, Oviedo, FL (US);

Kevin Matocha, El Dorado, AR (US);

Sujit Banerjee, San Jose, CA (US);

Larry Burton Rowland, Scotia, NY (US);

Assignee:

Monolith Semiconductor Inc., Round Rock, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0623 (2013.01); H01L 29/0619 (2013.01); H01L 29/66712 (2013.01); H01L 29/66719 (2013.01); H01L 29/7802 (2013.01); H01L 29/7813 (2013.01); H01L 29/0696 (2013.01); H01L 29/0878 (2013.01); H01L 29/1095 (2013.01); H01L 29/42368 (2013.01); H01L 29/42376 (2013.01);
Abstract

Metal-oxide-semiconductor field-effect transistor (MOSFET) devices are described which have a p-type region between the p-type well regions of the device. The p-type region can be either floating or connected to the p-type well regions by additional p-type regions. MOSFET devices are also described which have one or more p-type regions connecting the p-type well regions of the device. The p-type well regions can be arranged in a various geometric arrangements including square, diamond and hexagonal. Methods of making the devices are also described.


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