The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2018

Filed:

Dec. 09, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Ruilong Xie, Schenectady, NY (US);

Murat Kerem Akarvardar, Saratoga Springs, NY (US);

Andreas Knorr, Wappingers Falls, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/10 (2006.01); H01L 21/3105 (2006.01); H01L 21/321 (2006.01); H01L 21/762 (2006.01); H01L 21/308 (2006.01); H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823821 (2013.01); H01L 21/3083 (2013.01); H01L 21/3105 (2013.01); H01L 21/32105 (2013.01); H01L 21/76224 (2013.01); H01L 21/823807 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01); H01L 29/1054 (2013.01); H01L 29/7849 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/7842 (2013.01);
Abstract

A method of forming SRB finFET fins first with a cut mask that is perpendicular to the subsequent fin direction and then with a cut mask that is parallel to the fin direction and the resulting device are provided. Embodiments include forming a SiGe SRB on a substrate; forming a Si layer over the SRB; forming an NFET channel and a SiGe PFET channel in the Si layer; forming cuts through the NFET and PFET channels, respectively, and the SRB down to the substrate, the cuts formed on opposite ends of the substrate and perpendicular to the NFET and PFET channels; forming fins in the SRB and the NFET and PFET channels, the fins formed perpendicular to the cuts; forming a cut between the NFET and PFET channels, the cut formed parallel to the fins; filling the cut with oxide; and recessing the oxide down to the SRB.


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