The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2018

Filed:

Jun. 01, 2016
Applicant:

Kla-tencor Corporation, Milpitas, CA (US);

Inventors:

Ajay Gupta, Cupertino, CA (US);

Thanh Huy Ha, Milpitas, CA (US);

Olivier Moreau, Sunnyvale, CA (US);

Kumar Raja, Concord, CA (US);

Assignee:

KLA-Tencor Corp., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/00 (2006.01); H01L 21/76 (2006.01); G01B 11/00 (2006.01); H01L 23/544 (2006.01); G06F 19/00 (2018.01); H01J 37/22 (2006.01); G03F 7/20 (2006.01);
U.S. Cl.
CPC ...
H01J 37/222 (2013.01); G03F 7/70633 (2013.01); H01J 2237/221 (2013.01); H01J 2237/24578 (2013.01); H01J 2237/31798 (2013.01);
Abstract

Methods and systems for determining overlay error between different patterned features of a design printed on a wafer in a multi-patterning step process are provided. For multi-patterning step designs, the design for a first patterning step is used as a reference and designs for each of the remaining patterning steps are synthetically shifted until the synthetically shifted designs have the best global alignment with the entire image based on global image-to-design alignment. The final synthetic shift of each design for each patterning step relative to the design for the first patterning step provides a measurement of relative overlay error between any two features printed on the wafer using multi-patterning technology.


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