The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2018
Filed:
Oct. 27, 2015
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventors:
Hideki Makiyama, Tokyo, JP;
Yoshiki Yamamoto, Tokyo, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01); H01L 29/0684 (2013.01); H01L 29/42356 (2013.01); H01L 29/66545 (2013.01); H01L 21/82385 (2013.01); H01L 21/823814 (2013.01); H01L 21/823878 (2013.01);
Abstract
The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.