The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Feb. 04, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY (US);

Inventors:

Edward C. Cooney, III, Jericho, VT (US);

Gary L. Milo, Milton, VT (US);

Thomas W. Weeks, Hyde Park, VT (US);

Patrick S. Spinney, Charlotte, VT (US);

John C. Hall, Essex Junction, VT (US);

Brian P. Conchieri, Essex, VT (US);

Brett T. Cucci, Essex Junction, VT (US);

Thomas C. Lee, Essex Junction, VT (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 23/544 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
H01L 22/32 (2013.01); G01R 31/2853 (2013.01); G01R 31/2884 (2013.01); H01L 23/544 (2013.01);
Abstract

Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.


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