The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Nov. 21, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu OT, TW;

Inventors:

Wei-Shuo Ho, New Taipei, TW;

Tsung-Yu Chiang, New Taipei, TW;

Kuang-Hsin Chen, Jung-Li, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/283 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H01L 21/324 (2006.01); H01L 21/768 (2006.01); H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/0214 (2013.01); H01L 21/02164 (2013.01); H01L 21/283 (2013.01); H01L 21/30604 (2013.01); H01L 21/31144 (2013.01); H01L 21/324 (2013.01); H01L 21/76804 (2013.01); H01L 21/823456 (2013.01); H01L 21/823481 (2013.01); H01L 27/0207 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/4916 (2013.01); H01L 29/518 (2013.01); H01L 29/6681 (2013.01); H01L 29/7851 (2013.01);
Abstract

A method of manufacturing a semiconductor structure includes receiving a substrate; patterning a first active region, a second active region and an isolation between the first active region and the second active region over the substrate; disposing an inter-level dielectric (ILD) over the substrate; forming a first gate extended over the first active region, the isolation and the second active region; and forming a second gate over the first active region and the second active region, wherein the second gate includes a first section disposed over the first active region and a second section disposed over the second active region, a portion of the ILD is disposed between the first section and the second section.


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