Method to improve floating gate uniformity for non-volatile memory device

Abstract

The present disclosure relates a method for manufacturing an integrated circuit. In some embodiments, a semiconductor substrate is provided and made up of a memory array region and a boundary region surrounding the memory array region. A hard mask layer is formed over the memory array region and the boundary region. The hard mask layer is patterned to form a boundary hard mask having one or more slots to expose some portions of the boundary region while the remaining regions of the boundary region are covered by the boundary hard mask. A floating gate layer is formed within the memory array region and extending over the hard mask layer. Then, a planarization is performed to reduce a height of the floating gate layer and form a plurality of floating gates.