The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

Feb. 27, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kalyan Kavalipurapu, Santa Clara, CA (US);

Allahyar Vahidimowlavi, San Jose, CA (US);

Erwin Yu, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 11/4076 (2006.01); G11C 11/56 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G06F 3/061 (2013.01); G06F 3/0625 (2013.01); G06F 3/0655 (2013.01); G06F 3/0688 (2013.01); G11C 11/4076 (2013.01); G11C 11/5628 (2013.01); G11C 16/3445 (2013.01); G11C 16/3454 (2013.01); G11C 2211/5621 (2013.01);
Abstract

Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to initiate a program verify sequence to verify data written to a non-volatile memory (NVM). The program verify sequence can have one or more program verify levels that each correspond to memory cells in the NVM for which written data is being verified. The memory controller can detect an approximate percentage of memory cells for each program verify level in which data is successfully written. The memory controller can determine to skip subsequent program pulse verification checks in one or more program verify levels when the approximate percentage of memory cells in which data is successfully written is less than a defined threshold.


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