The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

Dec. 19, 2016
Applicants:

Da Woon Jeong, Hwaseong-si, KR;

Sung-hun Lee, Yongin-si, KR;

Seokjung Yun, Iksan-si, KR;

Hyunmog Park, Seoul, KR;

Joongshik Shin, Yongin-si, KR;

Young-bae Yoon, Hwaseong-si, KR;

Inventors:

Da Woon Jeong, Hwaseong-si, KR;

Sung-Hun Lee, Yongin-si, KR;

Seokjung Yun, Iksan-si, KR;

Hyunmog Park, Seoul, KR;

JoongShik Shin, Yongin-si, KR;

Young-Bae Yoon, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); G11C 16/04 (2006.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 21/768 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); G11C 5/025 (2013.01); G11C 5/06 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01);
Abstract

Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.


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