The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2018

Filed:

Apr. 15, 2016
Applicant:

Kinsus Interconnect Technology Corp., Taoyuan, TW;

Inventors:

Ting-Hao Lin, Taoyuan, TW;

Chiao-Cheng Chang, Taoyuan, TW;

Yi-Nong Lin, Taoyuan, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01K 3/10 (2006.01); H05K 1/11 (2006.01); H05K 3/18 (2006.01); H05K 3/42 (2006.01); H05K 3/00 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 1/115 (2013.01); H05K 3/0047 (2013.01); H05K 3/0079 (2013.01); H05K 3/0094 (2013.01); H05K 3/18 (2013.01); H05K 3/429 (2013.01); H05K 3/4644 (2013.01); Y10T 29/49165 (2015.01);
Abstract

Provided is a landless multilayer circuit board and a manufacturing method thereof. The manufacturing method includes steps of forming a first circuit on a first substrate, patterning a photoresist layer to form at least one via between the first circuit and a second circuit, forming at least one connecting pillar in the at least one via, removing the photoresist layer, forming a second substrate to cover the at least one connect pillar, and forming the second circuit on the second substrate. The second circuit is connected to the first circuit through the at least one connecting pillar. When the second circuit is formed, the at least one via does not need to be filled, thereby making the second circuit flat.


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