The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2018

Filed:

Jan. 26, 2017
Applicant:

Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;

Inventors:

Chien Lin Chang Chien, Kaohsiung, TW;

Chang Chi Lee, Kaohsiung, TW;

Chin-Li Kao, Kaohsiung, TW;

Dao-Long Chen, Kaohsiung, TW;

Ta-Chien Cheng, Kaohsiung, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/3121 (2013.01); H01L 23/3135 (2013.01); H01L 23/3672 (2013.01); H01L 24/33 (2013.01); H01L 25/50 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06589 (2013.01);
Abstract

A semiconductor device package includes a package substrate, a first electronic device, a second electronic device and a first molding layer. The package substrate includes a first surface, a second surface opposite to the first surface, and an edge. The first electronic device is positioned over and electrically connected to the package substrate through the first surface. The second electronic device is positioned over and electrically connected to the first electronic device. The first molding layer is positioned over the package substrate, and the first molding layer encapsulates a portion of the first surface and the edge of the package substrate.


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