The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2018

Filed:

Apr. 27, 2017
Applicants:

Keung Beum Kim, Hwaseong-si, KR;

Hyunjong Moon, Seoul, KR;

Seung-yong Cha, Hwaseong-si, KR;

Inventors:

Keung Beum Kim, Hwaseong-si, KR;

Hyunjong Moon, Seoul, KR;

Seung-Yong Cha, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 25/10 (2006.01); H01L 23/522 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/11 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5227 (2013.01); H01L 23/3128 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 24/09 (2013.01); H01L 24/46 (2013.01); H01L 25/105 (2013.01); H01L 25/117 (2013.01); H01L 25/50 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/14131 (2013.01); H01L 2224/48091 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/107 (2013.01); H01L 2225/1017 (2013.01); H05K 2201/10378 (2013.01);
Abstract

A semiconductor package includes a first package and a second package stacked on the first package. The first package includes a redistribution substrate, a first semiconductor chip on the redistribution substrate, a connection substrate provided on the redistribution substrate to surround the first semiconductor chip as viewed in plan, and an inductor structure provided within a first region of the connection substrate and electrically connected to the first semiconductor chip through the redistribution substrate. The second package includes at least one outer terminal electrically connected to the first package. The outer terminal is provided on a second region of the connection substrate, and when viewed in plan, the first region and the second region are spaced apart from each other.


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